Not sure why there is so much resistance to this technology. The work is already done, Core 2 already contains all the technology required to implement this new feature.
1) L2 cache is shared and does not require bus access to read/write.
2) Single FSB shared by both cores.
3) Cores can be dynamically enabled/disabled.
4) L2 cache can be dynamically assigned.
5) Individual execution units can be dynamically powered-up and down.
Source:XS Post#21
No comments:
Post a Comment