Last week Intel held a press event at its main quarter office in Santa Clara, California. Intel displayed its 1 Teraflops chip whose 80 core design has been discussed in earlier reports. Except from the mighty multithreading monster code-named "tera-scale silicon prototype", there was also a lot of talk about power consumption and efficiency. That the performance increase with every generation is a given, but how the power consumption and power efficiency evolves is not as predictable. Intel is continuously working on new technology to improve the efficiency of the circuits, thus lowering the power consumption and it revealed some of its newest progress at the event.
"A prototype of the technology was demonstrated in a PCI Express card with a chip that consumed one-tenth the power of a card with today's chip technology, or 2.7 milliwatts versus 20 to 30 milliwatts. Reducing power consumption is critical, given that using today's technology to power a PCI Express card with a bandwidth of a terabit per second would require 100 watts of energy, Casper said."
The basic idea is that Intel wants every chip to use precisely the amount of power necessary to perform a given task. Intel has been looking at wireless circuits and been able to reduce the power consumption by up to 50% to 70% by shutting off the Wi-Fi circuits when it's not needed.
Over at InformationWeek there is a longer report on Intel's press event where they also bring up the UMPC concept and other ventures.
Source:Intel talks future chips, power, efficiency and mobility